The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components and passive components.
Integrated CMOS circuits produced by present-day conventional processes suffer from the disadvantage that the passive components required in the circuit, such as coils and capacitors, have a low Q-factor when used in typical high frequency applications such as input stages for symmetrical mixers or impedance transformers. This low Q-factor is attributable to undesirable capacitive coupling, and to the generation of eddy currents flowing in the conducting semiconductor substrate, made possible by the great number of charge carriers existing in such a semiconductor substrate.
Passive components with a low Q-factor are not desirable in high frequency circuits, since they require the use of additional active stages, in order to compensate for the energy losses caused on account of the low Q-factor. In addition to this, the use of components with a low Q-factor results in increased noise figures. However, and in particular in the case of CMOS circuits, the use of passive components is unavoidable because the CMOS components present a strictly capacitive input impedance, so that normally a coil with a high inductivity must be used, for the purpose of impedance matching, which acts in series-resonance with the input capacitance of the MOS transistor. In such a typical application, in particular, the low Q-factor with which the coil can be produced, is of great disadvantage.
The aim of the invention is to provide an integrated CMOS circuit for use at high frequencies, wherein passive components with a high Q-factor can be produced by a simple and cost-effective process.
In accordance with the invention, this aim is achieved in that the active CMOS components are formed in a semiconductor substrate which has a specific resistivity in the order of magnitude of kxcexa9cm, that a buried layer is arranged under the active CMOS components in the semiconductor substrate, which has a specific resistivity in the order of magnitude of xcexa9cm, that the passive components are arranged in or on a layer of insulating material deposited on the semiconductor substrate, and that a conducting contact layer is provided on the surface of the semiconductor substrate not facing the layer of insulating material.
The integrated CMOS circuit according to the invention is formed in a high-resistance substrate with a conductive contact layer on the other side. The buried conductive layer created under the CMOS components, that is the active components of the circuit, prevents undesirable latch-up effects caused by any parasitic thyristor action. This conductive buried layer does not exist under the passive components, to prevent this from being the cause of coupling with neighboring components. It is no longer possible for eddy currents, induced by the passive components, to be created to a significant degree, as the required charge carriers are bled off through the conductive contact layer.
Advantageous further embodiments of the invention are indicated in the sub-claims.